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<title>DM-CtrlH7-BF-DevProgram: C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h File Reference</title>
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<div class="header">
  <div class="headertitle"><div class="title">stm32h7xx_hal_spi.h File Reference</div></div>
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<p>Header file of SPI HAL module.  
<a href="#details">More...</a></p>
<div class="textblock"><code>#include &quot;<a class="el" href="stm32h7xx__hal__def_8h_source.html">stm32h7xx_hal_def.h</a>&quot;</code><br />
<code>#include &quot;<a class="el" href="stm32h7xx__hal__spi__ex_8h_source.html">stm32h7xx_hal_spi_ex.h</a>&quot;</code><br />
</div>
<p><a href="stm32h7xx__hal__spi_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-nested-classes" class="groupheader"><a id="nested-classes" name="nested-classes"></a>
Classes</h2></td></tr>
<tr class="memitem:SPI_5FInitTypeDef" id="r_SPI_5FInitTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_p_i___init_type_def.html">SPI_InitTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI Configuration Structure definition.  <a href="struct_s_p_i___init_type_def.html#details">More...</a><br /></td></tr>
<tr class="memitem:_5F_5FSPI_5FHandleTypeDef" id="r__5F_5FSPI_5FHandleTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_____s_p_i___handle_type_def.html">__SPI_HandleTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI handle Structure definition.  <a href="struct_____s_p_i___handle_type_def.html#details">More...</a><br /></td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-define-members" class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga713834e556cbf0b498835b76c934726e" id="r_ga713834e556cbf0b498835b76c934726e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_LOWEND_FIFO_SIZE</b>&#160;&#160;&#160;8UL</td></tr>
<tr class="memitem:ga61e8c28ab72b549b82ee1fbc553bcaec" id="r_ga61e8c28ab72b549b82ee1fbc553bcaec"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_HIGHEND_FIFO_SIZE</b>&#160;&#160;&#160;16UL</td></tr>
<tr class="memitem:gaac0006cdf5670741f8702e55d4bf4601" id="r_gaac0006cdf5670741f8702e55d4bf4601"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#gaac0006cdf5670741f8702e55d4bf4601">HAL_SPI_ERROR_NONE</a>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga75f5edd4e2a7a95bc9a994244df52460" id="r_ga75f5edd4e2a7a95bc9a994244df52460"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#ga75f5edd4e2a7a95bc9a994244df52460">HAL_SPI_ERROR_MODF</a>&#160;&#160;&#160;(0x00000001UL)</td></tr>
<tr class="memitem:gad1163823ec5fa89e4670366565d4ab93" id="r_gad1163823ec5fa89e4670366565d4ab93"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#gad1163823ec5fa89e4670366565d4ab93">HAL_SPI_ERROR_CRC</a>&#160;&#160;&#160;(0x00000002UL)</td></tr>
<tr class="memitem:ga9587f998fed196a4f30c38f2da731c0f" id="r_ga9587f998fed196a4f30c38f2da731c0f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#ga9587f998fed196a4f30c38f2da731c0f">HAL_SPI_ERROR_OVR</a>&#160;&#160;&#160;(0x00000004UL)</td></tr>
<tr class="memitem:gaf03238e57dd0c4d277fef2aa7a083133" id="r_gaf03238e57dd0c4d277fef2aa7a083133"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#gaf03238e57dd0c4d277fef2aa7a083133">HAL_SPI_ERROR_FRE</a>&#160;&#160;&#160;(0x00000008UL)</td></tr>
<tr class="memitem:gaaf91992131301e3fc7f2ce62fb011f6c" id="r_gaaf91992131301e3fc7f2ce62fb011f6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#gaaf91992131301e3fc7f2ce62fb011f6c">HAL_SPI_ERROR_DMA</a>&#160;&#160;&#160;(0x00000010UL)</td></tr>
<tr class="memitem:ga777b36b52caf926a384976baf34530a3" id="r_ga777b36b52caf926a384976baf34530a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#ga777b36b52caf926a384976baf34530a3">HAL_SPI_ERROR_FLAG</a>&#160;&#160;&#160;(0x00000020UL)</td></tr>
<tr class="memitem:gab7fa15838d5ef9316ed8a0ec1c782fb7" id="r_gab7fa15838d5ef9316ed8a0ec1c782fb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#gab7fa15838d5ef9316ed8a0ec1c782fb7">HAL_SPI_ERROR_ABORT</a>&#160;&#160;&#160;(0x00000040UL)</td></tr>
<tr class="memitem:ga58d86c21484e1d1fe3027ec2771706cc" id="r_ga58d86c21484e1d1fe3027ec2771706cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#ga58d86c21484e1d1fe3027ec2771706cc">HAL_SPI_ERROR_UDR</a>&#160;&#160;&#160;(0x00000080UL)</td></tr>
<tr class="memitem:ga67dd5b4fb30d2e506e5900261eec47ba" id="r_ga67dd5b4fb30d2e506e5900261eec47ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#ga67dd5b4fb30d2e506e5900261eec47ba">HAL_SPI_ERROR_TIMEOUT</a>&#160;&#160;&#160;(0x00000100UL)</td></tr>
<tr class="memitem:ga81d13d9d60c821fea6f2e993e656f92a" id="r_ga81d13d9d60c821fea6f2e993e656f92a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#ga81d13d9d60c821fea6f2e993e656f92a">HAL_SPI_ERROR_UNKNOW</a>&#160;&#160;&#160;(0x00000200UL)</td></tr>
<tr class="memitem:ga4e6d9b12a40b3c6ac209f0e711ba3397" id="r_ga4e6d9b12a40b3c6ac209f0e711ba3397"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#ga4e6d9b12a40b3c6ac209f0e711ba3397">HAL_SPI_ERROR_NOT_SUPPORTED</a>&#160;&#160;&#160;(0x00000400UL)</td></tr>
<tr class="memitem:gacc0d4d1cc59ba95a075fd6244505d4ed" id="r_gacc0d4d1cc59ba95a075fd6244505d4ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___error___code.html#gacc0d4d1cc59ba95a075fd6244505d4ed">HAL_SPI_ERROR_RELOAD</a>&#160;&#160;&#160;(0x00000800UL)</td></tr>
<tr class="memitem:ga75f094fee5a9dc10b88401ccd17925d3" id="r_ga75f094fee5a9dc10b88401ccd17925d3"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MODE_SLAVE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:gaa335c2abdfad9e6f6c2677719d93b64e" id="r_gaa335c2abdfad9e6f6c2677719d93b64e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MODE_MASTER</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gae374f7d95b2b790e5741a84932b8c63f">SPI_CFG2_MASTER</a></td></tr>
<tr class="memitem:gaa7cb7f4bf4eebbf91bcfaeb17ebba7f3" id="r_gaa7cb7f4bf4eebbf91bcfaeb17ebba7f3"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DIRECTION_2LINES</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga0882de57168be019d97078fc9a017414" id="r_ga0882de57168be019d97078fc9a017414"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DIRECTION_2LINES_TXONLY</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gab19c27afabbaf50a9e02e2aa0f489383">SPI_CFG2_COMM_0</a></td></tr>
<tr class="memitem:ga444826cf94667f75503f54704b2fb391" id="r_ga444826cf94667f75503f54704b2fb391"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DIRECTION_2LINES_RXONLY</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga8577b6cfe88294c5f4326d795338b252">SPI_CFG2_COMM_1</a></td></tr>
<tr class="memitem:gab0f684caf5f1d6ac1e73d90a4778ab93" id="r_gab0f684caf5f1d6ac1e73d90a4778ab93"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DIRECTION_1LINE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga1b7bf18425d7ade65a2e772fde619bf1">SPI_CFG2_COMM</a></td></tr>
<tr class="memitem:ga333dd776c2e5bd34a62ec2c778e79b31" id="r_ga333dd776c2e5bd34a62ec2c778e79b31"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_4BIT</b>&#160;&#160;&#160;(0x00000003UL)</td></tr>
<tr class="memitem:gac419892f10e003ca1610b02764a9571a" id="r_gac419892f10e003ca1610b02764a9571a"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_5BIT</b>&#160;&#160;&#160;(0x00000004UL)</td></tr>
<tr class="memitem:ga4ae84231733c205f5824fd04411f4256" id="r_ga4ae84231733c205f5824fd04411f4256"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_6BIT</b>&#160;&#160;&#160;(0x00000005UL)</td></tr>
<tr class="memitem:ga255495a4ed0b621c7febc3381cc126a3" id="r_ga255495a4ed0b621c7febc3381cc126a3"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_7BIT</b>&#160;&#160;&#160;(0x00000006UL)</td></tr>
<tr class="memitem:ga773e9fc5d44c9661c829361fbd073152" id="r_ga773e9fc5d44c9661c829361fbd073152"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_8BIT</b>&#160;&#160;&#160;(0x00000007UL)</td></tr>
<tr class="memitem:ga5aaa20dba9ccfa33b21b5b0412b3b9a4" id="r_ga5aaa20dba9ccfa33b21b5b0412b3b9a4"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_9BIT</b>&#160;&#160;&#160;(0x00000008UL)</td></tr>
<tr class="memitem:ga45f9441b23fa3975e6a66329e3edc540" id="r_ga45f9441b23fa3975e6a66329e3edc540"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_10BIT</b>&#160;&#160;&#160;(0x00000009UL)</td></tr>
<tr class="memitem:gac89fef02c2b72a45f0d9bd4b9108464f" id="r_gac89fef02c2b72a45f0d9bd4b9108464f"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_11BIT</b>&#160;&#160;&#160;(0x0000000AUL)</td></tr>
<tr class="memitem:ga6156f3714711c5aa25444cb0db4de48e" id="r_ga6156f3714711c5aa25444cb0db4de48e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_12BIT</b>&#160;&#160;&#160;(0x0000000BUL)</td></tr>
<tr class="memitem:ga99da120c51ef48974fea4a9da210184c" id="r_ga99da120c51ef48974fea4a9da210184c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_13BIT</b>&#160;&#160;&#160;(0x0000000CUL)</td></tr>
<tr class="memitem:gac9b8f5abf1d7d31f2d814e5f19546df9" id="r_gac9b8f5abf1d7d31f2d814e5f19546df9"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_14BIT</b>&#160;&#160;&#160;(0x0000000DUL)</td></tr>
<tr class="memitem:ga36b5ba62b97fae23c1162a87b256ca45" id="r_ga36b5ba62b97fae23c1162a87b256ca45"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_15BIT</b>&#160;&#160;&#160;(0x0000000EUL)</td></tr>
<tr class="memitem:ga902147b9ead27cd9333240c72ce74f59" id="r_ga902147b9ead27cd9333240c72ce74f59"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_16BIT</b>&#160;&#160;&#160;(0x0000000FUL)</td></tr>
<tr class="memitem:gaa5b7c0d07ea4c989dcf890f213027069" id="r_gaa5b7c0d07ea4c989dcf890f213027069"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_17BIT</b>&#160;&#160;&#160;(0x00000010UL)</td></tr>
<tr class="memitem:ga90e8bf9c20f3541edcce58020043251e" id="r_ga90e8bf9c20f3541edcce58020043251e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_18BIT</b>&#160;&#160;&#160;(0x00000011UL)</td></tr>
<tr class="memitem:ga3ea8fde428541f2f04d7bef222c5cb61" id="r_ga3ea8fde428541f2f04d7bef222c5cb61"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_19BIT</b>&#160;&#160;&#160;(0x00000012UL)</td></tr>
<tr class="memitem:ga45fb19e55af484730cf125cd6b07d01b" id="r_ga45fb19e55af484730cf125cd6b07d01b"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_20BIT</b>&#160;&#160;&#160;(0x00000013UL)</td></tr>
<tr class="memitem:ga7b5efe19cefe5db7d97ea2727f0f7556" id="r_ga7b5efe19cefe5db7d97ea2727f0f7556"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_21BIT</b>&#160;&#160;&#160;(0x00000014UL)</td></tr>
<tr class="memitem:ga6acc458ac0e424391a7c46af45760342" id="r_ga6acc458ac0e424391a7c46af45760342"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_22BIT</b>&#160;&#160;&#160;(0x00000015UL)</td></tr>
<tr class="memitem:gad96bf29323a77a7e19e4d5aa9a2ef79c" id="r_gad96bf29323a77a7e19e4d5aa9a2ef79c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_23BIT</b>&#160;&#160;&#160;(0x00000016UL)</td></tr>
<tr class="memitem:gaafee8ba14a71379532b56e2d1ef87553" id="r_gaafee8ba14a71379532b56e2d1ef87553"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_24BIT</b>&#160;&#160;&#160;(0x00000017UL)</td></tr>
<tr class="memitem:gae71ae631dc989b01d10e8a1cce86f932" id="r_gae71ae631dc989b01d10e8a1cce86f932"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_25BIT</b>&#160;&#160;&#160;(0x00000018UL)</td></tr>
<tr class="memitem:ga3e748283a9b23d681197eaa1d00a937c" id="r_ga3e748283a9b23d681197eaa1d00a937c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_26BIT</b>&#160;&#160;&#160;(0x00000019UL)</td></tr>
<tr class="memitem:gaf92dd54a953e20687b3f7d83c85a951c" id="r_gaf92dd54a953e20687b3f7d83c85a951c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_27BIT</b>&#160;&#160;&#160;(0x0000001AUL)</td></tr>
<tr class="memitem:ga9efafafe4361af128b1e4d74155005cf" id="r_ga9efafafe4361af128b1e4d74155005cf"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_28BIT</b>&#160;&#160;&#160;(0x0000001BUL)</td></tr>
<tr class="memitem:ga8b9d031b602a90193189482a7db1dffe" id="r_ga8b9d031b602a90193189482a7db1dffe"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_29BIT</b>&#160;&#160;&#160;(0x0000001CUL)</td></tr>
<tr class="memitem:gab46e03d8ef20500b8f1f98a2d669b5bf" id="r_gab46e03d8ef20500b8f1f98a2d669b5bf"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_30BIT</b>&#160;&#160;&#160;(0x0000001DUL)</td></tr>
<tr class="memitem:ga6b7f030988d003a5f556def47d6aca93" id="r_ga6b7f030988d003a5f556def47d6aca93"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_31BIT</b>&#160;&#160;&#160;(0x0000001EUL)</td></tr>
<tr class="memitem:ga308080800ba91a05c117ea93ada4517f" id="r_ga308080800ba91a05c117ea93ada4517f"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_DATASIZE_32BIT</b>&#160;&#160;&#160;(0x0000001FUL)</td></tr>
<tr class="memitem:gaf61e3c6ec671baef099516265793c8df" id="r_gaf61e3c6ec671baef099516265793c8df"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_POLARITY_LOW</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga6910e2527b7511eb3a55946b9b775cff" id="r_ga6910e2527b7511eb3a55946b9b775cff"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_POLARITY_HIGH</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaf9e5874b94f69e2af8d7fd460ff33460">SPI_CFG2_CPOL</a></td></tr>
<tr class="memitem:ga208be78b79c51df200a495c4d2110b57" id="r_ga208be78b79c51df200a495c4d2110b57"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_PHASE_1EDGE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga960275ac1d01d302c48e713399990c36" id="r_ga960275ac1d01d302c48e713399990c36"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_PHASE_2EDGE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga268bfe1b80b116394eef88b75cd3bcbd">SPI_CFG2_CPHA</a></td></tr>
<tr class="memitem:ga0bf14691b9d03eb158f190cefa7ab8fc" id="r_ga0bf14691b9d03eb158f190cefa7ab8fc"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_NSS_SOFT</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gad0e7364142f9a7eb6b5c59897dd8b72d">SPI_CFG2_SSM</a></td></tr>
<tr class="memitem:ga62c42a5e28ce3b0dc92c5186c10accf8" id="r_ga62c42a5e28ce3b0dc92c5186c10accf8"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_NSS_HARD_INPUT</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:gab7f2da432661406a37fa2afe4efacd87" id="r_gab7f2da432661406a37fa2afe4efacd87"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_NSS_HARD_OUTPUT</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga9c9863c4e8e013e090efbe2cc7d82c45">SPI_CFG2_SSOE</a></td></tr>
<tr class="memitem:ga34736b4ea038be7723b31a0416a26832" id="r_ga34736b4ea038be7723b31a0416a26832"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_NSS_PULSE_DISABLE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:gac6243661f7fabde22ef936590f88be78" id="r_gac6243661f7fabde22ef936590f88be78"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_NSS_PULSE_ENABLE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabe0131b6501f637fa0168c031050818d">SPI_CFG2_SSOM</a></td></tr>
<tr class="memitem:ga3c1e615518e705b8120f164ff4c1968e" id="r_ga3c1e615518e705b8120f164ff4c1968e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_BAUDRATEPRESCALER_2</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga807568c52b5ba449d7a2b1b85549db24" id="r_ga807568c52b5ba449d7a2b1b85549db24"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_BAUDRATEPRESCALER_4</b>&#160;&#160;&#160;(0x10000000UL)</td></tr>
<tr class="memitem:ga2393359eb495f95163206e17194f4847" id="r_ga2393359eb495f95163206e17194f4847"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_BAUDRATEPRESCALER_8</b>&#160;&#160;&#160;(0x20000000UL)</td></tr>
<tr class="memitem:gad6a08d920ad4ee524cf55cd09e4c4d0e" id="r_gad6a08d920ad4ee524cf55cd09e4c4d0e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_BAUDRATEPRESCALER_16</b>&#160;&#160;&#160;(0x30000000UL)</td></tr>
<tr class="memitem:ga53fda39d29f04b815f525b7f8c8dd9c2" id="r_ga53fda39d29f04b815f525b7f8c8dd9c2"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_BAUDRATEPRESCALER_32</b>&#160;&#160;&#160;(0x40000000UL)</td></tr>
<tr class="memitem:ga64129361cbd23907d14144befe2209f4" id="r_ga64129361cbd23907d14144befe2209f4"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_BAUDRATEPRESCALER_64</b>&#160;&#160;&#160;(0x50000000UL)</td></tr>
<tr class="memitem:ga939117a1ff97fbf4f1340cbb3141fb29" id="r_ga939117a1ff97fbf4f1340cbb3141fb29"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_BAUDRATEPRESCALER_128</b>&#160;&#160;&#160;(0x60000000UL)</td></tr>
<tr class="memitem:ga4debd0953aeeb470eae28a42aa8289c2" id="r_ga4debd0953aeeb470eae28a42aa8289c2"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_BAUDRATEPRESCALER_256</b>&#160;&#160;&#160;(0x70000000UL)</td></tr>
<tr class="memitem:ga2280ac1a6ed587b516419b5df6a8ea55" id="r_ga2280ac1a6ed587b516419b5df6a8ea55"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIRSTBIT_MSB</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga8b608690a1adf9df40f271c228a479a3" id="r_ga8b608690a1adf9df40f271c228a479a3"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIRSTBIT_LSB</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaaff6b7fae6de0289fd47beb27c3120b9">SPI_CFG2_LSBFRST</a></td></tr>
<tr class="memitem:gaffbf066ee656a4d56b75fa721a2eabcd" id="r_gaffbf066ee656a4d56b75fa721a2eabcd"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_TIMODE_DISABLE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga8b31d4b25f951edd1dfd7cf6d4387517" id="r_ga8b31d4b25f951edd1dfd7cf6d4387517"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_TIMODE_ENABLE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaa2a319d6039b6cc10375d0100979616b">SPI_CFG2_SP_0</a></td></tr>
<tr class="memitem:ga9cd586b66473d7f207103a443280820e" id="r_ga9cd586b66473d7f207103a443280820e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRCCALCULATION_DISABLE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga431d368997c9c41e8923cbcd41b00123" id="r_ga431d368997c9c41e8923cbcd41b00123"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRCCALCULATION_ENABLE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga25e56eef69334cb723e24a8d33fb0ef5">SPI_CFG1_CRCEN</a></td></tr>
<tr class="memitem:ga2c09210b093323a8e84af832657568ce" id="r_ga2c09210b093323a8e84af832657568ce"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_DATASIZE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga5896919382c681967077db5989600987" id="r_ga5896919382c681967077db5989600987"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_4BIT</b>&#160;&#160;&#160;(0x00030000UL)</td></tr>
<tr class="memitem:ga60abe77aaf271d7405046a573349438c" id="r_ga60abe77aaf271d7405046a573349438c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_5BIT</b>&#160;&#160;&#160;(0x00040000UL)</td></tr>
<tr class="memitem:gad6a6bca17e89cbdd62ca2109bb3363d0" id="r_gad6a6bca17e89cbdd62ca2109bb3363d0"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_6BIT</b>&#160;&#160;&#160;(0x00050000UL)</td></tr>
<tr class="memitem:ga4bfa535670ae39d1bd231486de4a7c76" id="r_ga4bfa535670ae39d1bd231486de4a7c76"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_7BIT</b>&#160;&#160;&#160;(0x00060000UL)</td></tr>
<tr class="memitem:ga9340cbde2576d63c53c3ee50d3303886" id="r_ga9340cbde2576d63c53c3ee50d3303886"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_8BIT</b>&#160;&#160;&#160;(0x00070000UL)</td></tr>
<tr class="memitem:ga45e985743dc6ac6d4f7c95e3d37e77b5" id="r_ga45e985743dc6ac6d4f7c95e3d37e77b5"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_9BIT</b>&#160;&#160;&#160;(0x00080000UL)</td></tr>
<tr class="memitem:ga74a9c6010643c7a1b3e98998191de28b" id="r_ga74a9c6010643c7a1b3e98998191de28b"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_10BIT</b>&#160;&#160;&#160;(0x00090000UL)</td></tr>
<tr class="memitem:ga20913de644d09499c5f34f970a6b7e7b" id="r_ga20913de644d09499c5f34f970a6b7e7b"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_11BIT</b>&#160;&#160;&#160;(0x000A0000UL)</td></tr>
<tr class="memitem:ga4cea5b3defecec2a324953790d89080a" id="r_ga4cea5b3defecec2a324953790d89080a"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_12BIT</b>&#160;&#160;&#160;(0x000B0000UL)</td></tr>
<tr class="memitem:gac0f3a6d93387ba39c14bdf7defa17453" id="r_gac0f3a6d93387ba39c14bdf7defa17453"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_13BIT</b>&#160;&#160;&#160;(0x000C0000UL)</td></tr>
<tr class="memitem:ga9d68e445a3e83ccda033f49102efd13d" id="r_ga9d68e445a3e83ccda033f49102efd13d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_14BIT</b>&#160;&#160;&#160;(0x000D0000UL)</td></tr>
<tr class="memitem:ga23e390ec3a1f86caffff1df959fe995d" id="r_ga23e390ec3a1f86caffff1df959fe995d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_15BIT</b>&#160;&#160;&#160;(0x000E0000UL)</td></tr>
<tr class="memitem:ga780edaa0a72a79c4d0fa9618541aaad8" id="r_ga780edaa0a72a79c4d0fa9618541aaad8"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_16BIT</b>&#160;&#160;&#160;(0x000F0000UL)</td></tr>
<tr class="memitem:ga603e5f7350646a1a3dd3e5bc07511558" id="r_ga603e5f7350646a1a3dd3e5bc07511558"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_17BIT</b>&#160;&#160;&#160;(0x00100000UL)</td></tr>
<tr class="memitem:ga1f3d15d9135ecec9f86d931978ae08c1" id="r_ga1f3d15d9135ecec9f86d931978ae08c1"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_18BIT</b>&#160;&#160;&#160;(0x00110000UL)</td></tr>
<tr class="memitem:ga50e5a97a65d5f37bb5bb43ea41f77b65" id="r_ga50e5a97a65d5f37bb5bb43ea41f77b65"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_19BIT</b>&#160;&#160;&#160;(0x00120000UL)</td></tr>
<tr class="memitem:ga5e775752dfbfe3814938e2f145b051aa" id="r_ga5e775752dfbfe3814938e2f145b051aa"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_20BIT</b>&#160;&#160;&#160;(0x00130000UL)</td></tr>
<tr class="memitem:ga53164ca307565dd4a7a8d19f480d6905" id="r_ga53164ca307565dd4a7a8d19f480d6905"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_21BIT</b>&#160;&#160;&#160;(0x00140000UL)</td></tr>
<tr class="memitem:gafa637661910cbe222b23d0e9ab895104" id="r_gafa637661910cbe222b23d0e9ab895104"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_22BIT</b>&#160;&#160;&#160;(0x00150000UL)</td></tr>
<tr class="memitem:ga104518dc78f33261d343e2ffabfcfa91" id="r_ga104518dc78f33261d343e2ffabfcfa91"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_23BIT</b>&#160;&#160;&#160;(0x00160000UL)</td></tr>
<tr class="memitem:ga23206c5e1910b162964a77fda4ddaf42" id="r_ga23206c5e1910b162964a77fda4ddaf42"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_24BIT</b>&#160;&#160;&#160;(0x00170000UL)</td></tr>
<tr class="memitem:ga874a9846781bf4dfcf51e19aec490ca8" id="r_ga874a9846781bf4dfcf51e19aec490ca8"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_25BIT</b>&#160;&#160;&#160;(0x00180000UL)</td></tr>
<tr class="memitem:ga0c23f85afbf9cf8e85803b89be2de01a" id="r_ga0c23f85afbf9cf8e85803b89be2de01a"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_26BIT</b>&#160;&#160;&#160;(0x00190000UL)</td></tr>
<tr class="memitem:gad2c651331b806491f615ccdf47236d4f" id="r_gad2c651331b806491f615ccdf47236d4f"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_27BIT</b>&#160;&#160;&#160;(0x001A0000UL)</td></tr>
<tr class="memitem:ga727fa0b5450eff21852ddea5619feb5c" id="r_ga727fa0b5450eff21852ddea5619feb5c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_28BIT</b>&#160;&#160;&#160;(0x001B0000UL)</td></tr>
<tr class="memitem:ga06fbfb6ca55129212d155b5facfb7ff5" id="r_ga06fbfb6ca55129212d155b5facfb7ff5"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_29BIT</b>&#160;&#160;&#160;(0x001C0000UL)</td></tr>
<tr class="memitem:ga304db958461e34a23b3cd810906e50fd" id="r_ga304db958461e34a23b3cd810906e50fd"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_30BIT</b>&#160;&#160;&#160;(0x001D0000UL)</td></tr>
<tr class="memitem:ga45edd7b346f6d5ac6568f5b7f41cd781" id="r_ga45edd7b346f6d5ac6568f5b7f41cd781"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_31BIT</b>&#160;&#160;&#160;(0x001E0000UL)</td></tr>
<tr class="memitem:ga8df89ae4fda57e6c9f3d2cd6e4793aee" id="r_ga8df89ae4fda57e6c9f3d2cd6e4793aee"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_LENGTH_32BIT</b>&#160;&#160;&#160;(0x001F0000UL)</td></tr>
<tr class="memitem:gab7d9ca7b317ea0b8953bdaa3ab98fb25" id="r_gab7d9ca7b317ea0b8953bdaa3ab98fb25"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_01DATA</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:gaf280553e1bb7b4f12a51a2868c539b5d" id="r_gaf280553e1bb7b4f12a51a2868c539b5d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_02DATA</b>&#160;&#160;&#160;(0x00000020UL)</td></tr>
<tr class="memitem:gac4004c7d60886b4b733a6466f4bdbd00" id="r_gac4004c7d60886b4b733a6466f4bdbd00"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_03DATA</b>&#160;&#160;&#160;(0x00000040UL)</td></tr>
<tr class="memitem:gadb2e232a6b95a4b9720573a92230adfa" id="r_gadb2e232a6b95a4b9720573a92230adfa"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_04DATA</b>&#160;&#160;&#160;(0x00000060UL)</td></tr>
<tr class="memitem:gae20c1d4fbc016b9be462dafe2b2520e0" id="r_gae20c1d4fbc016b9be462dafe2b2520e0"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_05DATA</b>&#160;&#160;&#160;(0x00000080UL)</td></tr>
<tr class="memitem:ga339814d9f97978ec90c3a59aef607094" id="r_ga339814d9f97978ec90c3a59aef607094"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_06DATA</b>&#160;&#160;&#160;(0x000000A0UL)</td></tr>
<tr class="memitem:ga93488d4fd4f688475fba29cdf7109b59" id="r_ga93488d4fd4f688475fba29cdf7109b59"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_07DATA</b>&#160;&#160;&#160;(0x000000C0UL)</td></tr>
<tr class="memitem:ga2ea3e15fd9641d2e379129d264646c93" id="r_ga2ea3e15fd9641d2e379129d264646c93"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_08DATA</b>&#160;&#160;&#160;(0x000000E0UL)</td></tr>
<tr class="memitem:ga887df02d8abccc6cdc9a1092ccb3402d" id="r_ga887df02d8abccc6cdc9a1092ccb3402d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_09DATA</b>&#160;&#160;&#160;(0x00000100UL)</td></tr>
<tr class="memitem:ga8f2cc6a174534aae4a2a03587cd054f9" id="r_ga8f2cc6a174534aae4a2a03587cd054f9"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_10DATA</b>&#160;&#160;&#160;(0x00000120UL)</td></tr>
<tr class="memitem:ga52808587f41978015ff3b9801df5a654" id="r_ga52808587f41978015ff3b9801df5a654"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_11DATA</b>&#160;&#160;&#160;(0x00000140UL)</td></tr>
<tr class="memitem:ga556d86b7cee3c9e483b1c922071b8cae" id="r_ga556d86b7cee3c9e483b1c922071b8cae"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_12DATA</b>&#160;&#160;&#160;(0x00000160UL)</td></tr>
<tr class="memitem:gae819e7ef9414e3ab38569e4f70ed081b" id="r_gae819e7ef9414e3ab38569e4f70ed081b"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_13DATA</b>&#160;&#160;&#160;(0x00000180UL)</td></tr>
<tr class="memitem:ga5a5f658c36df3263d419c66d34e48318" id="r_ga5a5f658c36df3263d419c66d34e48318"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_14DATA</b>&#160;&#160;&#160;(0x000001A0UL)</td></tr>
<tr class="memitem:ga63fdb6145b289860592d9624b6476f09" id="r_ga63fdb6145b289860592d9624b6476f09"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_15DATA</b>&#160;&#160;&#160;(0x000001C0UL)</td></tr>
<tr class="memitem:ga23f4641e65a3a7be37d1082180627fab" id="r_ga23f4641e65a3a7be37d1082180627fab"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FIFO_THRESHOLD_16DATA</b>&#160;&#160;&#160;(0x000001E0UL)</td></tr>
<tr class="memitem:gac3d377a56aa7c69f21a6880f83c314b0" id="r_gac3d377a56aa7c69f21a6880f83c314b0"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:gae4cd6ea8bcf65b9f19789e2cabe5e781" id="r_gae4cd6ea8bcf65b9f19789e2cabe5e781"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN</b>&#160;&#160;&#160;(0x00000001UL)</td></tr>
<tr class="memitem:ga1a43e2095f7f608768c348f4ee27efb3" id="r_ga1a43e2095f7f608768c348f4ee27efb3"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_NSS_POLARITY_LOW</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga86ba2010e94d80831c276d037aa097b9" id="r_ga86ba2010e94d80831c276d037aa097b9"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_NSS_POLARITY_HIGH</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaa1829b079924734042d20b1671fecc1d">SPI_CFG2_SSIOP</a></td></tr>
<tr class="memitem:gaf24ff7880e5eed4cf128e508c6e04c2e" id="r_gaf24ff7880e5eed4cf128e508c6e04c2e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_KEEP_IO_STATE_DISABLE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga0004a0ddf766e6d1e5814f0f9b6abcce" id="r_ga0004a0ddf766e6d1e5814f0f9b6abcce"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_KEEP_IO_STATE_ENABLE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaf0d90225cbbced8ab5c382605500e6b8">SPI_CFG2_AFCNTR</a></td></tr>
<tr class="memitem:gadd6423ea72ef07ab2bfb7c932f673a38" id="r_gadd6423ea72ef07ab2bfb7c932f673a38"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IO_SWAP_DISABLE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga7314b6ab695d88f2ac88b4181e8036bb" id="r_ga7314b6ab695d88f2ac88b4181e8036bb"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IO_SWAP_ENABLE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga6a392a021319a1e0fdf422502cfa47f2">SPI_CFG2_IOSWP</a></td></tr>
<tr class="memitem:gaebc308a70d2339b90974d34b38dbc43d" id="r_gaebc308a70d2339b90974d34b38dbc43d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_00CYCLE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:gad5fc55ad5a446f9706c3d54476b512f8" id="r_gad5fc55ad5a446f9706c3d54476b512f8"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_01CYCLE</b>&#160;&#160;&#160;(0x00000001UL)</td></tr>
<tr class="memitem:ga7204156acfb384d6c21e5cf6ea306c45" id="r_ga7204156acfb384d6c21e5cf6ea306c45"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_02CYCLE</b>&#160;&#160;&#160;(0x00000002UL)</td></tr>
<tr class="memitem:gabfb29d80616ec2405c69aecc17503828" id="r_gabfb29d80616ec2405c69aecc17503828"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_03CYCLE</b>&#160;&#160;&#160;(0x00000003UL)</td></tr>
<tr class="memitem:gafea666a1d3ba2b2f27f543f3b7cccf7d" id="r_gafea666a1d3ba2b2f27f543f3b7cccf7d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_04CYCLE</b>&#160;&#160;&#160;(0x00000004UL)</td></tr>
<tr class="memitem:ga89f368ded90081f16605835aab5bce35" id="r_ga89f368ded90081f16605835aab5bce35"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_05CYCLE</b>&#160;&#160;&#160;(0x00000005UL)</td></tr>
<tr class="memitem:ga8a33b27304975649b24696b89cd20f88" id="r_ga8a33b27304975649b24696b89cd20f88"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_06CYCLE</b>&#160;&#160;&#160;(0x00000006UL)</td></tr>
<tr class="memitem:ga875a2240eeee2ea937bae6ceef0a20af" id="r_ga875a2240eeee2ea937bae6ceef0a20af"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_07CYCLE</b>&#160;&#160;&#160;(0x00000007UL)</td></tr>
<tr class="memitem:ga1e2f9e70a6ac957aa66f1d0bf536e50e" id="r_ga1e2f9e70a6ac957aa66f1d0bf536e50e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_08CYCLE</b>&#160;&#160;&#160;(0x00000008UL)</td></tr>
<tr class="memitem:gacb985a4ebc50c344f2b5210a47ff43eb" id="r_gacb985a4ebc50c344f2b5210a47ff43eb"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_09CYCLE</b>&#160;&#160;&#160;(0x00000009UL)</td></tr>
<tr class="memitem:ga8c7263873cc0759366a1c2c54ef3595c" id="r_ga8c7263873cc0759366a1c2c54ef3595c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_10CYCLE</b>&#160;&#160;&#160;(0x0000000AUL)</td></tr>
<tr class="memitem:ga8eef34fb226a312f808e0fa953a6c6da" id="r_ga8eef34fb226a312f808e0fa953a6c6da"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_11CYCLE</b>&#160;&#160;&#160;(0x0000000BUL)</td></tr>
<tr class="memitem:ga4e7db53c89ade412a7f3a2c2ad0bbb18" id="r_ga4e7db53c89ade412a7f3a2c2ad0bbb18"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_12CYCLE</b>&#160;&#160;&#160;(0x0000000CUL)</td></tr>
<tr class="memitem:ga2cc6bd6c72cb7794559a79f82aad6f28" id="r_ga2cc6bd6c72cb7794559a79f82aad6f28"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_13CYCLE</b>&#160;&#160;&#160;(0x0000000DUL)</td></tr>
<tr class="memitem:gaa66a617b833b5174f7bfe0599b071d71" id="r_gaa66a617b833b5174f7bfe0599b071d71"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_14CYCLE</b>&#160;&#160;&#160;(0x0000000EUL)</td></tr>
<tr class="memitem:gad8e9ae667259021b9d99e695ec931c78" id="r_gad8e9ae667259021b9d99e695ec931c78"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_SS_IDLENESS_15CYCLE</b>&#160;&#160;&#160;(0x0000000FUL)</td></tr>
<tr class="memitem:ga4853acf2ce1d0d05c1c24cc8fded40f1" id="r_ga4853acf2ce1d0d05c1c24cc8fded40f1"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_00CYCLE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga9a7722df8332f6577cfd9b62122b6dba" id="r_ga9a7722df8332f6577cfd9b62122b6dba"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_01CYCLE</b>&#160;&#160;&#160;(0x00000010UL)</td></tr>
<tr class="memitem:gac5584efbd235b7e5b51fdefdbcae9726" id="r_gac5584efbd235b7e5b51fdefdbcae9726"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_02CYCLE</b>&#160;&#160;&#160;(0x00000020UL)</td></tr>
<tr class="memitem:ga1dbbbaeb1a4f4f2552986ef8a007e542" id="r_ga1dbbbaeb1a4f4f2552986ef8a007e542"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_03CYCLE</b>&#160;&#160;&#160;(0x00000030UL)</td></tr>
<tr class="memitem:gada3ca38ef15650b0751970b95df97fff" id="r_gada3ca38ef15650b0751970b95df97fff"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_04CYCLE</b>&#160;&#160;&#160;(0x00000040UL)</td></tr>
<tr class="memitem:gadac5c3d4e15cefabb3e3157b05539d73" id="r_gadac5c3d4e15cefabb3e3157b05539d73"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_05CYCLE</b>&#160;&#160;&#160;(0x00000050UL)</td></tr>
<tr class="memitem:gaf878b5baff1f6f5e77e939908b08d8b0" id="r_gaf878b5baff1f6f5e77e939908b08d8b0"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_06CYCLE</b>&#160;&#160;&#160;(0x00000060UL)</td></tr>
<tr class="memitem:ga79489f8c8e7c26d3dc9938feb9a7fc06" id="r_ga79489f8c8e7c26d3dc9938feb9a7fc06"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_07CYCLE</b>&#160;&#160;&#160;(0x00000070UL)</td></tr>
<tr class="memitem:ga9944e2e6ec91bf019a75eabacad10b13" id="r_ga9944e2e6ec91bf019a75eabacad10b13"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_08CYCLE</b>&#160;&#160;&#160;(0x00000080UL)</td></tr>
<tr class="memitem:ga6b0a1aae31aa185a16a8c9b82fcab832" id="r_ga6b0a1aae31aa185a16a8c9b82fcab832"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_09CYCLE</b>&#160;&#160;&#160;(0x00000090UL)</td></tr>
<tr class="memitem:gaa8d7ef1738423c941ce170773adef684" id="r_gaa8d7ef1738423c941ce170773adef684"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_10CYCLE</b>&#160;&#160;&#160;(0x000000A0UL)</td></tr>
<tr class="memitem:ga9919558b939858382990caae904d3333" id="r_ga9919558b939858382990caae904d3333"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_11CYCLE</b>&#160;&#160;&#160;(0x000000B0UL)</td></tr>
<tr class="memitem:ga35e94b1a9d874b18e7e9e7ba6f56dbec" id="r_ga35e94b1a9d874b18e7e9e7ba6f56dbec"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_12CYCLE</b>&#160;&#160;&#160;(0x000000C0UL)</td></tr>
<tr class="memitem:ga5737924e39436d92b2bd2aafeaa39ded" id="r_ga5737924e39436d92b2bd2aafeaa39ded"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_13CYCLE</b>&#160;&#160;&#160;(0x000000D0UL)</td></tr>
<tr class="memitem:ga9984eea55812f477cf919460fd222ff3" id="r_ga9984eea55812f477cf919460fd222ff3"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_14CYCLE</b>&#160;&#160;&#160;(0x000000E0UL)</td></tr>
<tr class="memitem:gad46552fc29844cfa12319a7d6fc21d0d" id="r_gad46552fc29844cfa12319a7d6fc21d0d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_INTERDATA_IDLENESS_15CYCLE</b>&#160;&#160;&#160;(0x000000F0UL)</td></tr>
<tr class="memitem:gabb61d71ba4bbab92eebdb44a49fbe104" id="r_gabb61d71ba4bbab92eebdb44a49fbe104"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_RX_AUTOSUSP_DISABLE</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:gad5ed38df1f0eabbcbca154e84d392a80" id="r_gad5ed38df1f0eabbcbca154e84d392a80"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_MASTER_RX_AUTOSUSP_ENABLE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gae7d399759fc0606d8ef44845004a9faf">SPI_CR1_MASRX</a></td></tr>
<tr class="memitem:ga0c404920cb066c09e68cda6d77623c8c" id="r_ga0c404920cb066c09e68cda6d77623c8c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_UNDERRUN_BEHAV_REGISTER_PATTERN</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga649197985c765c0444b0c23317dcae66" id="r_ga649197985c765c0444b0c23317dcae66"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_UNDERRUN_BEHAV_LAST_RECEIVED</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaa77dbb8777fc83d62910a7775b26870b">SPI_CFG1_UDRCFG_0</a></td></tr>
<tr class="memitem:ga805e0687bf914dbce3a5a8c5ed13a7a6" id="r_ga805e0687bf914dbce3a5a8c5ed13a7a6"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaa2ef84d2d59adad7d35f91769218fcd5">SPI_CFG1_UDRCFG_1</a></td></tr>
<tr class="memitem:gae4c0607921a6cb1ffb06f69c39610725" id="r_gae4c0607921a6cb1ffb06f69c39610725"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME</b>&#160;&#160;&#160;(0x00000000UL)</td></tr>
<tr class="memitem:ga01e2b7f6968e6435f6e837d6657f5310" id="r_ga01e2b7f6968e6435f6e837d6657f5310"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_UNDERRUN_DETECT_END_DATA_FRAME</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga7fbc8512d964f194d96bba1e5dd7582f">SPI_CFG1_UDRDET_0</a></td></tr>
<tr class="memitem:ga7e490521724455f9829722c4114d9325" id="r_ga7e490521724455f9829722c4114d9325"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaced6f95340b0146aa0f172f766f1b92c">SPI_CFG1_UDRDET_1</a></td></tr>
<tr class="memitem:ga2ac4437f5e914d2a67cc2defcfc602fd" id="r_ga2ac4437f5e914d2a67cc2defcfc602fd"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_RXP</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga87b292843107573ae82aa13d88916646">SPI_IER_RXPIE</a></td></tr>
<tr class="memitem:ga85330ea17907191083c4abe2c1ee2bdd" id="r_ga85330ea17907191083c4abe2c1ee2bdd"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_TXP</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga40ad06dce5bd7f4f2d1db25e8ecd33a4">SPI_IER_TXPIE</a></td></tr>
<tr class="memitem:ga4ab7780c881917c14b466ff5b51612dd" id="r_ga4ab7780c881917c14b466ff5b51612dd"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_DXP</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga5fde811db0bae41847c2c56d20e1983b">SPI_IER_DXPIE</a></td></tr>
<tr class="memitem:gad10d2d33d7ca00b9e7f1ebe49b6e2680" id="r_gad10d2d33d7ca00b9e7f1ebe49b6e2680"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_EOT</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gadd814e85e0f2cc9fd5fbedbd1db232c1">SPI_IER_EOTIE</a></td></tr>
<tr class="memitem:ga7b9bb233a930cf959574a8e56ebf0518" id="r_ga7b9bb233a930cf959574a8e56ebf0518"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_TXTF</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaf329c2e8fb5112c4efdcac4c69bf95fb">SPI_IER_TXTFIE</a></td></tr>
<tr class="memitem:ga0ec21034e2bbe05a2ece43cadc2ed012" id="r_ga0ec21034e2bbe05a2ece43cadc2ed012"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_UDR</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga33d0436c4b553cc357b52b9ecaaf542f">SPI_IER_UDRIE</a></td></tr>
<tr class="memitem:gae99166c2b214fd7a9800a15eda36e4a0" id="r_gae99166c2b214fd7a9800a15eda36e4a0"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_OVR</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga6ba53086c19a3260e0555ace5d700c42">SPI_IER_OVRIE</a></td></tr>
<tr class="memitem:ga9aa97a5ce8d3500dc14ca4e30eada199" id="r_ga9aa97a5ce8d3500dc14ca4e30eada199"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_CRCERR</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga298b617fdd0e3d18562509839aa72fa3">SPI_IER_CRCEIE</a></td></tr>
<tr class="memitem:ga8500faddb159725ac374a8f761310bf7" id="r_ga8500faddb159725ac374a8f761310bf7"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_FRE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga07f63f1611444f70daf6b08fc18490ee">SPI_IER_TIFREIE</a></td></tr>
<tr class="memitem:ga0b9780d5f31fd80f4d0fa7d6860041e9" id="r_ga0b9780d5f31fd80f4d0fa7d6860041e9"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_MODF</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga6d05af6bd42d7191edec2763928dee98">SPI_IER_MODFIE</a></td></tr>
<tr class="memitem:ga48eaa446953bfa4b550764ada3499999" id="r_ga48eaa446953bfa4b550764ada3499999"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_TSERF</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga1a4844bc9d90e49ba0dcacf7787f2e16">SPI_IER_TSERFIE</a></td></tr>
<tr class="memitem:gace6a9377da7f18ea8b5c73163c2278d6" id="r_gace6a9377da7f18ea8b5c73163c2278d6"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_IT_ERR</b>&#160;&#160;&#160;(SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)</td></tr>
<tr class="memitem:ga9ba64b3cfed2459e105a1dd92dd52804" id="r_ga9ba64b3cfed2459e105a1dd92dd52804"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_RXP</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga95289b0733d92829f9f0189574dc1d54">SPI_SR_RXP</a>     /* SPI status flag : Rx-Packet available flag                 */</td></tr>
<tr class="memitem:gaee1560c53486464ea55f6404d1e4e31e" id="r_gaee1560c53486464ea55f6404d1e4e31e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_TXP</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga9f7199bbdd797f0238aaaf9cc42e4f64">SPI_SR_TXP</a>     /* SPI status flag : Tx-Packet space available flag           */</td></tr>
<tr class="memitem:ga1fea08c99d7432f2179ed6eed7628df2" id="r_ga1fea08c99d7432f2179ed6eed7628df2"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_DXP</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga73f785111c63d6e951018ebc0fffacf6">SPI_SR_DXP</a>     /* SPI status flag : Duplex Packet flag                       */</td></tr>
<tr class="memitem:ga1b76cc528b950514ee2432c456c73713" id="r_ga1b76cc528b950514ee2432c456c73713"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_EOT</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gadf6af11782cace2048e20c18d4d63e1a">SPI_SR_EOT</a>     /* SPI status flag : End of transfer flag                     */</td></tr>
<tr class="memitem:gaeba0c8020ffece1fc9f6ca27e2035935" id="r_gaeba0c8020ffece1fc9f6ca27e2035935"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_TXTF</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gac0e93a296bc722bab78d526bf1cc2f7d">SPI_SR_TXTF</a>    /* SPI status flag : Transmission Transfer Filled flag        */</td></tr>
<tr class="memitem:gabb6a58ae2fd5025950cab3d3a07e68af" id="r_gabb6a58ae2fd5025950cab3d3a07e68af"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_UDR</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga13d3292e963499c0e9a36869909229e6">SPI_SR_UDR</a>     /* SPI Error flag  : Underrun flag                            */</td></tr>
<tr class="memitem:gab45264da2296c75495a7437a045513ea" id="r_gab45264da2296c75495a7437a045513ea"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_OVR</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaa8d902302c5eb81ce4a57029de281232">SPI_SR_OVR</a>     /* SPI Error flag  : Overrun flag                             */</td></tr>
<tr class="memitem:ga30fb6af50e1f3c61cb9de76b0101c889" id="r_ga30fb6af50e1f3c61cb9de76b0101c889"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_CRCERR</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga4c0cf2db0d5d372242e66e6d7da50b39">SPI_SR_CRCE</a>    /* SPI Error flag  : CRC error flag                           */</td></tr>
<tr class="memitem:ga27dd114d8adc70f1439c054289f9313a" id="r_ga27dd114d8adc70f1439c054289f9313a"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_FRE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaf3e3c940fb46d8b32456c59819e615be">SPI_SR_TIFRE</a>   /* SPI Error flag  : TI mode frame format error flag          */</td></tr>
<tr class="memitem:gac7d3525ab98cc18f02270a4dba685897" id="r_gac7d3525ab98cc18f02270a4dba685897"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_MODF</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gabaa043349833dc7b8138969c64f63adf">SPI_SR_MODF</a>    /* SPI Error flag  : Mode fault flag                          */</td></tr>
<tr class="memitem:gaa28a29f609dbcef512f258e5c72d84b0" id="r_gaa28a29f609dbcef512f258e5c72d84b0"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_TSERF</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga5332b248a3daf660df7f13098e75da46">SPI_SR_TSERF</a>   /* SPI status flag : Additional number of data reloaded flag  */</td></tr>
<tr class="memitem:ga6a4b56fbf17d58ff9805441c5ab8a928" id="r_ga6a4b56fbf17d58ff9805441c5ab8a928"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_SUSP</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga3294b6597873bd2c0f2acb9e722e18cc">SPI_SR_SUSP</a>    /* SPI status flag : Transfer suspend complete flag           */</td></tr>
<tr class="memitem:ga1646c5ebd8e683ff26afdf029fb57cf8" id="r_ga1646c5ebd8e683ff26afdf029fb57cf8"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_TXC</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga1695e2f6e8d042aeae4d9f07e96dfe1a">SPI_SR_TXC</a>     /* SPI status flag : TxFIFO transmission complete flag        */</td></tr>
<tr class="memitem:ga4406c904711e73f41bfbc930bfc92d58" id="r_ga4406c904711e73f41bfbc930bfc92d58"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_FRLVL</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga09c4e3cd9a199757d6f3ac06e5bc110f">SPI_SR_RXPLVL</a>  /* SPI status flag : Fifo reception level flag                */</td></tr>
<tr class="memitem:gad87f2b93de239ba67ad4bfdc2774defb" id="r_gad87f2b93de239ba67ad4bfdc2774defb"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_FLAG_RXWNE</b>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gab6334377efffc8f2733962c827a4bf03">SPI_SR_RXWNE</a>   /* SPI status flag : RxFIFO word not empty flag               */</td></tr>
<tr class="memitem:gae6af55d98ad99eb4657a8c209a91e3ad" id="r_gae6af55d98ad99eb4657a8c209a91e3ad"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_RX_FIFO_0PACKET</b>&#160;&#160;&#160;(0x00000000UL)         /* 0 or multiple of 4 packets available in the RxFIFO */</td></tr>
<tr class="memitem:ga256694027539fe571c57602573150cbf" id="r_ga256694027539fe571c57602573150cbf"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_RX_FIFO_1PACKET</b>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga927d85d0857d7a63232e1668f30957b2">SPI_SR_RXPLVL_0</a>)</td></tr>
<tr class="memitem:gaa31f8bf709d8a7b8b17ca44f261abc7e" id="r_gaa31f8bf709d8a7b8b17ca44f261abc7e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_RX_FIFO_2PACKET</b>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga06d2c44cda484d3ac4dc9d81cf056183">SPI_SR_RXPLVL_1</a>)</td></tr>
<tr class="memitem:ga0ad493fbe3f6dffa865bfb3bbac55bed" id="r_ga0ad493fbe3f6dffa865bfb3bbac55bed"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_RX_FIFO_3PACKET</b>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga06d2c44cda484d3ac4dc9d81cf056183">SPI_SR_RXPLVL_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga927d85d0857d7a63232e1668f30957b2">SPI_SR_RXPLVL_0</a>)</td></tr>
<tr class="memitem:ga0d846f9517715960873e854b4a0790b0" id="r_ga0d846f9517715960873e854b4a0790b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga0d846f9517715960873e854b4a0790b0">__HAL_SPI_RESET_HANDLE_STATE</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga0d846f9517715960873e854b4a0790b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset SPI handle state.  <br /></td></tr>
<tr class="memitem:ga76064652f6f56d8868720b5541e854f5" id="r_ga76064652f6f56d8868720b5541e854f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga76064652f6f56d8868720b5541e854f5">__HAL_SPI_ENABLE_IT</a>(__HANDLE__,  __INTERRUPT__)</td></tr>
<tr class="memdesc:ga76064652f6f56d8868720b5541e854f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the specified SPI interrupts.  <br /></td></tr>
<tr class="memitem:ga47fa7321c5755bfbff1a7229fbe5b21c" id="r_ga47fa7321c5755bfbff1a7229fbe5b21c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga47fa7321c5755bfbff1a7229fbe5b21c">__HAL_SPI_DISABLE_IT</a>(__HANDLE__,  __INTERRUPT__)</td></tr>
<tr class="memdesc:ga47fa7321c5755bfbff1a7229fbe5b21c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the specified SPI interrupts.  <br /></td></tr>
<tr class="memitem:gabdaab061e4603331a0ec4b9d651df0b5" id="r_gabdaab061e4603331a0ec4b9d651df0b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#gabdaab061e4603331a0ec4b9d651df0b5">__HAL_SPI_GET_IT_SOURCE</a>(__HANDLE__,  __INTERRUPT__)</td></tr>
<tr class="memdesc:gabdaab061e4603331a0ec4b9d651df0b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether the specified SPI interrupt source is enabled or not.  <br /></td></tr>
<tr class="memitem:gaa0bbe5fb55f93fd277ddb6acf58cec53" id="r_gaa0bbe5fb55f93fd277ddb6acf58cec53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#gaa0bbe5fb55f93fd277ddb6acf58cec53">__HAL_SPI_GET_FLAG</a>(__HANDLE__,  __FLAG__)</td></tr>
<tr class="memdesc:gaa0bbe5fb55f93fd277ddb6acf58cec53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether the specified SPI flag is set or not.  <br /></td></tr>
<tr class="memitem:gad1cb4100b67726531ad426d300f4cd26" id="r_gad1cb4100b67726531ad426d300f4cd26"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#gad1cb4100b67726531ad426d300f4cd26">__HAL_SPI_CLEAR_CRCERRFLAG</a>(__HANDLE__)</td></tr>
<tr class="memdesc:gad1cb4100b67726531ad426d300f4cd26"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the SPI CRCERR pending flag.  <br /></td></tr>
<tr class="memitem:ga6c88becbe528c542156bc201622efba2" id="r_ga6c88becbe528c542156bc201622efba2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga6c88becbe528c542156bc201622efba2">__HAL_SPI_CLEAR_MODFFLAG</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga6c88becbe528c542156bc201622efba2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the SPI MODF pending flag.  <br /></td></tr>
<tr class="memitem:gaf6af33b1c5d334b9fe7bb778c5b6442e" id="r_gaf6af33b1c5d334b9fe7bb778c5b6442e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#gaf6af33b1c5d334b9fe7bb778c5b6442e">__HAL_SPI_CLEAR_OVRFLAG</a>(__HANDLE__)</td></tr>
<tr class="memdesc:gaf6af33b1c5d334b9fe7bb778c5b6442e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the SPI OVR pending flag.  <br /></td></tr>
<tr class="memitem:ga7ff182f5cf6c731318c882351d6d7ac2" id="r_ga7ff182f5cf6c731318c882351d6d7ac2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga7ff182f5cf6c731318c882351d6d7ac2">__HAL_SPI_CLEAR_FREFLAG</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga7ff182f5cf6c731318c882351d6d7ac2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the SPI FRE pending flag.  <br /></td></tr>
<tr class="memitem:ga788e7e6782849d79499064b05050627e" id="r_ga788e7e6782849d79499064b05050627e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga788e7e6782849d79499064b05050627e">__HAL_SPI_CLEAR_UDRFLAG</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga788e7e6782849d79499064b05050627e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the SPI UDR pending flag.  <br /></td></tr>
<tr class="memitem:ga82b82dd74c0fe69c823e92323fde890a" id="r_ga82b82dd74c0fe69c823e92323fde890a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga82b82dd74c0fe69c823e92323fde890a">__HAL_SPI_CLEAR_EOTFLAG</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga82b82dd74c0fe69c823e92323fde890a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the SPI EOT pending flag.  <br /></td></tr>
<tr class="memitem:gac4e14a47b0110348bb2edf1eb6023a50" id="r_gac4e14a47b0110348bb2edf1eb6023a50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#gac4e14a47b0110348bb2edf1eb6023a50">__HAL_SPI_CLEAR_TXTFFLAG</a>(__HANDLE__)</td></tr>
<tr class="memdesc:gac4e14a47b0110348bb2edf1eb6023a50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the SPI UDR pending flag.  <br /></td></tr>
<tr class="memitem:ga76cb5dc888df5c6d19675e4d076b750d" id="r_ga76cb5dc888df5c6d19675e4d076b750d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga76cb5dc888df5c6d19675e4d076b750d">__HAL_SPI_CLEAR_SUSPFLAG</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga76cb5dc888df5c6d19675e4d076b750d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the SPI SUSP pending flag.  <br /></td></tr>
<tr class="memitem:ga9a45859eee2e15a4a6367cc4a5066c8b" id="r_ga9a45859eee2e15a4a6367cc4a5066c8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga9a45859eee2e15a4a6367cc4a5066c8b">__HAL_SPI_CLEAR_TSERFFLAG</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga9a45859eee2e15a4a6367cc4a5066c8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the SPI TSERF pending flag.  <br /></td></tr>
<tr class="memitem:ga16d2d73c2b16004499ae8d492e71fd4e" id="r_ga16d2d73c2b16004499ae8d492e71fd4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#ga16d2d73c2b16004499ae8d492e71fd4e">__HAL_SPI_ENABLE</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga16d2d73c2b16004499ae8d492e71fd4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the SPI peripheral.  <br /></td></tr>
<tr class="memitem:gaa10d88f87d16de53bd81dfb33bd56959" id="r_gaa10d88f87d16de53bd81dfb33bd56959"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___macros.html#gaa10d88f87d16de53bd81dfb33bd56959">__HAL_SPI_DISABLE</a>(__HANDLE__)</td></tr>
<tr class="memdesc:gaa10d88f87d16de53bd81dfb33bd56959"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the SPI peripheral.  <br /></td></tr>
<tr class="memitem:gae3b2eb5e818e58b66474d42dedac5523" id="r_gae3b2eb5e818e58b66474d42dedac5523"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gae3b2eb5e818e58b66474d42dedac5523">SPI_1LINE_TX</a>(__HANDLE__)</td></tr>
<tr class="memdesc:gae3b2eb5e818e58b66474d42dedac5523"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the SPI transmit-only mode in 1Line configuration.  <br /></td></tr>
<tr class="memitem:gaa8d58cef91c1874d5a4dde4014cf6269" id="r_gaa8d58cef91c1874d5a4dde4014cf6269"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gaa8d58cef91c1874d5a4dde4014cf6269">SPI_1LINE_RX</a>(__HANDLE__)</td></tr>
<tr class="memdesc:gaa8d58cef91c1874d5a4dde4014cf6269"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the SPI receive-only mode in 1Line configuration.  <br /></td></tr>
<tr class="memitem:ga2e139e6f86af7b6f2690e679b0303162" id="r_ga2e139e6f86af7b6f2690e679b0303162"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga2e139e6f86af7b6f2690e679b0303162">SPI_2LINES_TX</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga2e139e6f86af7b6f2690e679b0303162"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the SPI transmit-only mode in 2Lines configuration.  <br /></td></tr>
<tr class="memitem:ga39089f4a0d840c0748936a574142c8fa" id="r_ga39089f4a0d840c0748936a574142c8fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga39089f4a0d840c0748936a574142c8fa">SPI_2LINES_RX</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga39089f4a0d840c0748936a574142c8fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the SPI receive-only mode in 2Lines configuration.  <br /></td></tr>
<tr class="memitem:ga5ff90af4675f015852b14e755ce79e08" id="r_ga5ff90af4675f015852b14e755ce79e08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga5ff90af4675f015852b14e755ce79e08">SPI_2LINES</a>(__HANDLE__)</td></tr>
<tr class="memdesc:ga5ff90af4675f015852b14e755ce79e08"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the SPI Transmit-Receive mode in 2Lines configuration.  <br /></td></tr>
<tr class="memitem:gad5135300763c75dbb446861536359f12" id="r_gad5135300763c75dbb446861536359f12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gad5135300763c75dbb446861536359f12">IS_SPI_MODE</a>(MODE)</td></tr>
<tr class="memitem:ga8ce4827db741ff965ea0cb1c105b00d5" id="r_ga8ce4827db741ff965ea0cb1c105b00d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga8ce4827db741ff965ea0cb1c105b00d5">IS_SPI_DIRECTION</a>(MODE)</td></tr>
<tr class="memitem:ga79454622381b22d02c8cdd3346c80f78" id="r_ga79454622381b22d02c8cdd3346c80f78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga79454622381b22d02c8cdd3346c80f78">IS_SPI_DIRECTION_2LINES</a>(MODE)</td></tr>
<tr class="memitem:ga28006c88236f1a94f4e69d9d868f21fe" id="r_ga28006c88236f1a94f4e69d9d868f21fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga28006c88236f1a94f4e69d9d868f21fe">IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY</a>(MODE)</td></tr>
<tr class="memitem:gad0d8a45ecf7ef088463d1b818bd09826" id="r_gad0d8a45ecf7ef088463d1b818bd09826"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gad0d8a45ecf7ef088463d1b818bd09826">IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY</a>(MODE)</td></tr>
<tr class="memitem:gab6f9f528f7eb70373b9caf3548e44e67" id="r_gab6f9f528f7eb70373b9caf3548e44e67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gab6f9f528f7eb70373b9caf3548e44e67">IS_SPI_DATASIZE</a>(DATASIZE)</td></tr>
<tr class="memitem:ga3f1e514b528933ad992018edcf97e23b" id="r_ga3f1e514b528933ad992018edcf97e23b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga3f1e514b528933ad992018edcf97e23b">IS_SPI_FIFOTHRESHOLD</a>(THRESHOLD)</td></tr>
<tr class="memitem:gafc1cc5b1ff7e801a409a7a1e6047acf9" id="r_gafc1cc5b1ff7e801a409a7a1e6047acf9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gafc1cc5b1ff7e801a409a7a1e6047acf9">IS_SPI_CPOL</a>(CPOL)</td></tr>
<tr class="memitem:ga6441f08edf79dd5b243c54b888d3cbf7" id="r_ga6441f08edf79dd5b243c54b888d3cbf7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga6441f08edf79dd5b243c54b888d3cbf7">IS_SPI_CPHA</a>(CPHA)</td></tr>
<tr class="memitem:gabbeedf42eccef1bae4f88c606fc3b261" id="r_gabbeedf42eccef1bae4f88c606fc3b261"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gabbeedf42eccef1bae4f88c606fc3b261">IS_SPI_NSS</a>(NSS)</td></tr>
<tr class="memitem:ga9bbb9935c81663db6b96a2cb08ef6006" id="r_ga9bbb9935c81663db6b96a2cb08ef6006"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga9bbb9935c81663db6b96a2cb08ef6006">IS_SPI_NSSP</a>(NSSP)</td></tr>
<tr class="memitem:gae79f46ed9f91e39dc1f6912cb25fc716" id="r_gae79f46ed9f91e39dc1f6912cb25fc716"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gae79f46ed9f91e39dc1f6912cb25fc716">IS_SPI_BAUDRATE_PRESCALER</a>(PRESCALER)</td></tr>
<tr class="memitem:gabee8e0302741f4a5c41b96af640c63ad" id="r_gabee8e0302741f4a5c41b96af640c63ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gabee8e0302741f4a5c41b96af640c63ad">IS_SPI_FIRST_BIT</a>(BIT)</td></tr>
<tr class="memitem:ga812f7bf5919bc6e45727d6ac05c60b49" id="r_ga812f7bf5919bc6e45727d6ac05c60b49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga812f7bf5919bc6e45727d6ac05c60b49">IS_SPI_TIMODE</a>(MODE)</td></tr>
<tr class="memitem:ga96e66460d09a553fd9996c53dcc4b252" id="r_ga96e66460d09a553fd9996c53dcc4b252"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga96e66460d09a553fd9996c53dcc4b252">IS_SPI_CRC_CALCULATION</a>(CALCULATION)</td></tr>
<tr class="memitem:gad39542cb3b654effe9c4e3d8079884ba" id="r_gad39542cb3b654effe9c4e3d8079884ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gad39542cb3b654effe9c4e3d8079884ba">IS_SPI_CRC_INITIALIZATION_PATTERN</a>(PATTERN)</td></tr>
<tr class="memitem:ga393003a5b035758f07c7243738c5f463" id="r_ga393003a5b035758f07c7243738c5f463"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga393003a5b035758f07c7243738c5f463">IS_SPI_CRC_LENGTH</a>(LENGTH)</td></tr>
<tr class="memitem:ga76eec5bbb44c873aa52966a9cb6c8f8c" id="r_ga76eec5bbb44c873aa52966a9cb6c8f8c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga76eec5bbb44c873aa52966a9cb6c8f8c">IS_SPI_CRC_POLYNOMIAL</a>(POLYNOMIAL)</td></tr>
<tr class="memitem:ga9bc863efd4059e29b055978c9eb36909" id="r_ga9bc863efd4059e29b055978c9eb36909"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga9bc863efd4059e29b055978c9eb36909">IS_SPI_CRC_POLYNOMIAL_SIZE</a>(POLYNOM,  LENGTH)</td></tr>
<tr class="memitem:ga17f299bb0d8e36dbeb43457a7c521328" id="r_ga17f299bb0d8e36dbeb43457a7c521328"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga17f299bb0d8e36dbeb43457a7c521328">IS_SPI_UNDERRUN_DETECTION</a>(MODE)</td></tr>
<tr class="memitem:gaa3d1fe42e2147532ac110d26904ebd32" id="r_gaa3d1fe42e2147532ac110d26904ebd32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#gaa3d1fe42e2147532ac110d26904ebd32">IS_SPI_UNDERRUN_BEHAVIOUR</a>(MODE)</td></tr>
<tr class="memitem:ga5810568855b1df12700af47c4c4fad61" id="r_ga5810568855b1df12700af47c4c4fad61"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___private___macros.html#ga5810568855b1df12700af47c4c4fad61">IS_SPI_MASTER_RX_AUTOSUSP</a>(MODE)</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-typedef-members" class="groupheader"><a id="typedef-members" name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:gab633e49dd034de2f3a1fe79853d78d18" id="r_gab633e49dd034de2f3a1fe79853d78d18"><td class="memItemLeft" align="right" valign="top">
typedef struct <a class="el" href="struct_____s_p_i___handle_type_def.html">__SPI_HandleTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>SPI_HandleTypeDef</b></td></tr>
<tr class="memdesc:gab633e49dd034de2f3a1fe79853d78d18"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI handle Structure definition. <br /></td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-enum-members" class="groupheader"><a id="enum-members" name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:ga8891cb64e76198a860172d94c638c9b4" id="r_ga8891cb64e76198a860172d94c638c9b4"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___types.html#ga8891cb64e76198a860172d94c638c9b4">HAL_SPI_StateTypeDef</a> { <br />
&#160;&#160;<a class="el" href="group___s_p_i___exported___types.html#gga8891cb64e76198a860172d94c638c9b4adbc218df2c9841b561282b40b3ded69d">HAL_SPI_STATE_RESET</a> = 0x00UL
, <a class="el" href="group___s_p_i___exported___types.html#gga8891cb64e76198a860172d94c638c9b4abb3992c67a15c14bd1808ef6b63fa926">HAL_SPI_STATE_READY</a> = 0x01UL
, <a class="el" href="group___s_p_i___exported___types.html#gga8891cb64e76198a860172d94c638c9b4a0635e168bc0430253fe8e74cfe9768fd">HAL_SPI_STATE_BUSY</a> = 0x02UL
, <a class="el" href="group___s_p_i___exported___types.html#gga8891cb64e76198a860172d94c638c9b4a5d82b644c7ca656ab5fe8a8e3cbc29ab">HAL_SPI_STATE_BUSY_TX</a> = 0x03UL
, <br />
&#160;&#160;<a class="el" href="group___s_p_i___exported___types.html#gga8891cb64e76198a860172d94c638c9b4afd7e00128aca1feaa099c2595ffb9277">HAL_SPI_STATE_BUSY_RX</a> = 0x04UL
, <a class="el" href="group___s_p_i___exported___types.html#gga8891cb64e76198a860172d94c638c9b4a9dae2883ae3e43ca28afc9453a14c938">HAL_SPI_STATE_BUSY_TX_RX</a> = 0x05UL
, <a class="el" href="group___s_p_i___exported___types.html#gga8891cb64e76198a860172d94c638c9b4a3cba266d2346abe3b62fa0acccab4711">HAL_SPI_STATE_ERROR</a> = 0x06UL
, <a class="el" href="group___s_p_i___exported___types.html#gga8891cb64e76198a860172d94c638c9b4a34f9231d040d752a034db85e3eb7f782">HAL_SPI_STATE_ABORT</a> = 0x07UL
<br />
 }</td></tr>
<tr class="memdesc:ga8891cb64e76198a860172d94c638c9b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">HAL SPI State structure definition.  <a href="group___s_p_i___exported___types.html#ga8891cb64e76198a860172d94c638c9b4">More...</a><br /></td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-func-members" class="groupheader"><a id="func-members" name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gaadb9d40e710c714d96b2501996658c44" id="r_gaadb9d40e710c714d96b2501996658c44"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_Init</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:gaca2db2a7bbed96ac013c565080fb61f2" id="r_gaca2db2a7bbed96ac013c565080fb61f2"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_DeInit</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga17f583be14b22caffa6c4e56dcd035ef" id="r_ga17f583be14b22caffa6c4e56dcd035ef"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___functions___group1.html#ga17f583be14b22caffa6c4e56dcd035ef">HAL_SPI_MspInit</a> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:gabadc4d4974af1afd943e8d13589068e1" id="r_gabadc4d4974af1afd943e8d13589068e1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___functions___group1.html#gabadc4d4974af1afd943e8d13589068e1">HAL_SPI_MspDeInit</a> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:gaca4b7bb29640435fb30d7eb89ce0fd62" id="r_gaca4b7bb29640435fb30d7eb89ce0fd62"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_Transmit</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)</td></tr>
<tr class="memitem:gafdf43dbe4e5ef225bed6650b6e8c6313" id="r_gafdf43dbe4e5ef225bed6650b6e8c6313"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_Receive</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)</td></tr>
<tr class="memitem:ga806db11431c61c963eb7ed8025e58f70" id="r_ga806db11431c61c963eb7ed8025e58f70"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_TransmitReceive</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)</td></tr>
<tr class="memitem:ga96859ed0a0b5571ecaa958780fb19700" id="r_ga96859ed0a0b5571ecaa958780fb19700"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_Transmit_IT</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi, const uint8_t *pData, uint16_t Size)</td></tr>
<tr class="memitem:gaaae0af2e2db7e7549b52b020a18f6168" id="r_gaaae0af2e2db7e7549b52b020a18f6168"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_Receive_IT</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi, uint8_t *pData, uint16_t Size)</td></tr>
<tr class="memitem:ga3bde00f3764556ef6050bea913269946" id="r_ga3bde00f3764556ef6050bea913269946"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_TransmitReceive_IT</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)</td></tr>
<tr class="memitem:gac48467984880755e9632f914e8576007" id="r_gac48467984880755e9632f914e8576007"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_Transmit_DMA</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi, const uint8_t *pData, uint16_t Size)</td></tr>
<tr class="memitem:ga626bb2ec54e7b6ff9bd5d807ae6e6e24" id="r_ga626bb2ec54e7b6ff9bd5d807ae6e6e24"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_Receive_DMA</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi, uint8_t *pData, uint16_t Size)</td></tr>
<tr class="memitem:gaf94b75cd52be2dc144867bd4be5f4a90" id="r_gaf94b75cd52be2dc144867bd4be5f4a90"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_TransmitReceive_DMA</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)</td></tr>
<tr class="memitem:ga61e4a628d6918ec838736d65ae135031" id="r_ga61e4a628d6918ec838736d65ae135031"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_DMAPause</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga7fdd4b7aa5c6bd560a476c833f546d93" id="r_ga7fdd4b7aa5c6bd560a476c833f546d93"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_DMAResume</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga7e01eb529af91fabc950180b927fa355" id="r_ga7e01eb529af91fabc950180b927fa355"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_DMAStop</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga11c74b1d91d88ff336f674f6376cc904" id="r_ga11c74b1d91d88ff336f674f6376cc904"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_Abort</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga75d7782876ed13b9f8aebfa8dbba5a1c" id="r_ga75d7782876ed13b9f8aebfa8dbba5a1c"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_Abort_IT</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:gaf3da6e0a87468bc039b578c21329df47" id="r_gaf3da6e0a87468bc039b578c21329df47"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_IRQHandler</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga0a99ab4f6aa6ee7dc2abca5483910dde" id="r_ga0a99ab4f6aa6ee7dc2abca5483910dde"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_TxCpltCallback</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga3df7021fe24cf874f8b1eec5bd5f4cb3" id="r_ga3df7021fe24cf874f8b1eec5bd5f4cb3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___functions___group2.html#ga3df7021fe24cf874f8b1eec5bd5f4cb3">HAL_SPI_RxCpltCallback</a> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memdesc:ga3df7021fe24cf874f8b1eec5bd5f4cb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">当SPI接收完成,将会调用此回调函数,可以进行协议解析或其他必须的数据处理等  <br /></td></tr>
<tr class="memitem:ga04e63f382f172164c8e7cae4ff5d883c" id="r_ga04e63f382f172164c8e7cae4ff5d883c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_p_i___exported___functions___group2.html#ga04e63f382f172164c8e7cae4ff5d883c">HAL_SPI_TxRxCpltCallback</a> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memdesc:ga04e63f382f172164c8e7cae4ff5d883c"><td class="mdescLeft">&#160;</td><td class="mdescRight">和RxCpltCallback共用解析即可,这里只是形式上封装一下,不用重复写 这是对HAL库的__weak函数的重写,传输使用IT或DMA模式,在传输完成时会调用此函数  <br /></td></tr>
<tr class="memitem:ga931ef2f7fd94ffa16ec431972b1b237f" id="r_ga931ef2f7fd94ffa16ec431972b1b237f"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_TxHalfCpltCallback</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:gacf622756a3814edfacf449b5749b048a" id="r_gacf622756a3814edfacf449b5749b048a"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_RxHalfCpltCallback</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:gab46e2325b0880d5b5a301792438b151b" id="r_gab46e2325b0880d5b5a301792438b151b"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_TxRxHalfCpltCallback</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga3db7835e7e7ac335887f62fedf156926" id="r_ga3db7835e7e7ac335887f62fedf156926"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_ErrorCallback</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga4a2593ec36fa4def11929e65f631f3cf" id="r_ga4a2593ec36fa4def11929e65f631f3cf"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_AbortCpltCallback</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga054dfb4bb84fa4d30cdad6915242e9d1" id="r_ga054dfb4bb84fa4d30cdad6915242e9d1"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_SuspendCallback</b> (<a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga3c57f63c08ced3c209dc61b8eea146ef" id="r_ga3c57f63c08ced3c209dc61b8eea146ef"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="group___s_p_i___exported___types.html#ga8891cb64e76198a860172d94c638c9b4">HAL_SPI_StateTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_GetState</b> (const <a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
<tr class="memitem:ga73e9fe6661ce972720f0364166775d32" id="r_ga73e9fe6661ce972720f0364166775d32"><td class="memItemLeft" align="right" valign="top">
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_SPI_GetError</b> (const <a class="el" href="group___s_p_i___exported___types.html#gab633e49dd034de2f3a1fe79853d78d18">SPI_HandleTypeDef</a> *hspi)</td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Header file of SPI HAL module. </p>
<dl class="section author"><dt>Author</dt><dd>MCD Application Team </dd></dl>
<dl class="section attention"><dt>Attention</dt><dd></dd></dl>
<p>Copyright (c) 2017 STMicroelectronics. All rights reserved.</p>
<p>This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS. </p>
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